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1/14 semiconductor msm5116400d 4,194,304-word 4-bit dynamic ram : fast page mode type description the msm5116400d is a 4,194,304-word 4-bit dynamic ram fabricated in okis silicon-gate cmos technology. the msm5116400d achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/double-layer metal cmos process. the msm5116400d is available in a 26/24-pin plastic soj, 26/24-pin plastic tsop. features 4,194,304-word 4-bit configuration single 5v power supply, 10% tolerance input : ttl compatible, low input capacitance output : ttl compatible, 3-state refresh : 4096 cycles/64 ms fast page mode, read modify write capability cas before ras refresh, hidden refresh, ras-only refresh capability multi-bit test mode capability package options: 26/24-pin 300mil plastic soj (soj26/24-p-300-1.27) (product : msm5116400d-xxsj) 26/24-pin 300mil plastic tsop (tsopii26/24-p-300-1.27-k) (product : msm5116400d-xxts-k) xx : indicates speed rank. product family access time (max.) power dissipation family t rac t aa t cac t oea cycle time (min.) operating (max.) standby (max.) msm5116400d-50 50ns 25ns 13ns 13ns 90ns 413mw MSM5116400D-60 60ns 30ns 15ns 15ns 110ns 385mw msm5116400d-70 70ns 35ns 20ns 20ns 130ns 358mw 5.5mw this version:apr.1999
msm5116400d 2/14 pin configration (top view) pin name function a0Ca11 address input ras row address strobe cas column address strobe dq1Cdq4 data input/data output oe output enable we write enable v cc power supply (5v) v ss ground (0v) nc no connection 26/24-pin plastic soj 26/24-pin plastic tsop (k type) 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 dq1 dq2 v cc v cc v ss v ss dq4 dq3 a9 a8 a7 a6 a0 a1 a2 a3 we ras a11 a10 a5 a4 cas oe 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 dq1 dq2 v cc v cc v ss v ss a9 a8 a7 a6 a0 a1 a2 a3 we ras a11 a10 a5 a4 oe dq4 dq3 cas
msm5116400d 3/14 block diagram a 0 C a 11 4 4 4 4 4 4 10 12 12 10 timing generator column address buffers internal address counter row address buffers refresh control clock column decoders sense amplifiers memory cells word drivers row deco- ders i/o selector input buffers output buffers dq 1 - dq 4 oe we ras cas v cc v ss on chip v bb generator timing generator 4 write clock generator
msm5116400d 4/14 electrical characteristics absolute maximum ratings parameter symbol rating unit voltage on any pin relative to v ss v t - 0.5 to 7.0 v short circuit output current i os 50 ma power dissipation p d* 1w operating temperature t opr 0 to 70 c storage temperature t stg - 55 to 150 c *: ta = 25c recommended operating conditions (ta = 0c to 70c) parameter symbol min. typ. max. unit v cc 4.5 5.0 5.5 v power supply voltage v ss 000v input high voltage v ih 2.4 ? v cc + 0.5 *1 v input low voltage v il - 0.5 *2 ? 0.8 v notes: *1. the input voltage is v cc + 2.0v when the pulse width is less than 20ns (the pulse width is with respect to the point at which v cc is applied). *2. the input voltage is v ss - 2.0v when the pulse width is less than 20ns (the pulse width respect to the point at which v ss is applied). capacitance (v cc = 5.0v 10%, ta = 25c, f=1mhz) parameter symbol typ. max. unit input capacitance (a0 C a11) c in1 ? 5pf input capacitance (ras, cas, we, oe) c in2 ? 7pf output capacitance (dq1 C dq4) c i/o ? 7pf
msm5116400d 5/14 dc characteristics (v cc = 5v 10%, ta = 0c to 70c) msm5116400 d-50 msm5116400 d-60 msm5116400 d-70 parameter symbol condition min. max min. max min. max unit note output high voltage v oh i oh = - 5.0ma 2.4 v cc 2.4 v cc 2.4 v cc v output low voltage v ol i ol = 4.2ma 00.400.400.4v input leakage current i li 0v v i 6.5v ; all other pins not under test = 0v - 10 10 - 10 10 - 10 10 m a output leakage current i lo dq disable 0v v o v cc - 10 10 - 10 10 - 10 10 m a average power supply current (operating) i cc1 ras, cas cycling, t rc = min. ? 75 ? 70 ? 65 ma 1,2 ras, cas = v ih ? 2 ? 2 ? 2 power supply current (standby) i cc2 ras, cas 3 v cc C 0.2v ? 0.5 ? 0.5 ? 0.5 ma 1 average power supply current (ras-only refresh) i cc3 ras cycling, cas = v ih , t rc = min. ? 75 ? 70 ? 65 ma 1,2 power supply current (standby) i cc5 ras = v ih , cas = v il , dq = enable ? 2 ? 2 ? 2ma1 average power supply current (cas before ras refresh) i cc6 ras = cycling, cas before ras ? 75 ? 70 ? 65 ma 1,2 average power supply current (fast page mode) i cc7 ras = v il , cas cycling, t pc = min. ? 70 ? 65 ? 60 ma 1,3 notes: 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih .
msm5116400d 6/14 ac characteristic (1/2) (v cc = 5v 10%, ta = 0c to 70c) note1,2,3 msm5116400 d-50 msm5116400 d-60 msm5116400 d-70 parameter symbol min. max. min. max. min. max. unit note random read or write cycle time t rc 90 ? 110 ? 130 ? ns read modify write cycle time t rwc 131 ? 155 ? 185 ? ns fast page mode cycle time t pc 35 ? 40 ? 45 ? ns fast page mode read modify write cycle time t prwc 76 ? 85 ? 100 ? ns access time from ras t rac ? 50 ? 60 ? 70 ns 4,5,6 access time from cas t cac ? 13 ? 15 ? 20 ns 4,5 access time from column address t aa ? 25 ? 30 ? 35 ns 4,6 access time from cas precharge t cpa ? 30 ? 35 ? 40 ns 4 access time from oe t oea ? 13 ? 15 ? 20 ns 4 output low impedance time from cas t clz 0 ? 0 ? 0 ? ns 4 cas to data output buffer turn- off delay time t off 013015020ns7 oe to data output buffer turn-off delay time t oez 013015020ns7 transition time t t 350350350ns3 refresh period t ref ? 64 ? 64 ? 64 m s ras precharge time t rp 30 ? 40 ? 50 ? ns ras pulse width t ras 50 10,000 60 10,000 70 10,000 ns ras pulse width (fast page mode) t rasp 50 100,000 60 100,000 70 100,000 ns ras hold time t rsh 13 ? 15 ? 20 ? ns ras hold time referenced to oe t roh 13 ? 15 ? 20 ? ns cas precharge time (fast page mode) t cp 7 ? 10 ? 10 ? ns cas pulse width t cas 13 10,000 15 10,000 20 10,000 ns cas hold time t csh 50 ? 60 ? 70 ? ns cas to ras precharge time t crp 5 ? 5 ? 5 ? ns ras hold time from cas precharge t rhcp 30 ? 35 ? 40 ? ns ras to cas delay time t rcd 17 37 20 45 20 50 ns 5 ras to column address delay time t rad 12 25 15 30 15 35 ns row address set-up time t asr 0 ? 0 ? 0 ? ns row address hold time t rah 7 ? 10 ? 10 ? ns column address set-up time t asc 0 ? 0 ? 0 ? ns
msm5116400d 7/14 ac characteristic (2/2) (v cc = 5v 10%, ta = 0c to 70c) note1,2,3 msm5116400 d-50 msm5116400 d-60 msm5116400 d-70 parameter symbol min. max. min. max. min. max. unit note column address hold time t cah 7 ? 15 ? 15 ? ns column address to ras lead time t ral 25 ? 30 ? 35 ? ns read command set-up time t rcs 0 ? 0 ? 0 ? ns read command hold time t rch 0 ? 0 ? 0 ? ns 8 read command hold time referenced to ras t rrh 0 ? 0 ? 0 ? ns 8 write command set-up time t wcs 0 ? 0 ? 0 ? ns 9 write command hold time t wch 7 ? 10 ? 15 ? ns write command pulse width t wp 7 ? 10 ? 10 ? ns oe command hold time t oeh 13 ? 15 ? 20 ? ns write command to ras lead time t rwl 13 ? 15 ? 20 ? ns write command to cas lead time t cwl 13 ? 15 ? 20 ? ns data-in set-up time t ds 0 ? 0 ? 0 ? ns 10 data-in hold time t dh 7 ? 10 ? 15 ? ns 10 oe to data-in delay time t oed 13 ? 15 ? 20 ? ns cas to we delay time t cwd 36 ? 40 ? 50 ? ns 9 column address to we delay time t awd 48 ? 55 ? 65 ? ns 9 ras to we delay time t rwd 73 ? 85 ? 100 ? ns 9 cas precharge we delay time t cpwd 53 ? 60 ? 70 ? ns 9 cas active delay time from ras precharge t rpc 5 ? 5 ? 5 ? ns ras to cas set-up time (cas before ras) t csr 10 ? 10 ? 10 ? ns ras to cas hold time (cas before ras) t chr 10 ? 10 ? 10 ? ns
msm5116400d 8/14 notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles (ras-only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl load and 100pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) and t oez (max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.), t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle.
msm5116400d 9/14 timing chart read cycle write cycle (early write) t wcs t wch t cwl t asr t rah t asc t crp t rp t rc t ras valid data-in t dh t rwl row t csh t crp t rcd t rsh t cas column t cah t rad t ral t ds t wp ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v ih v il h or l open t off t clz t cac t oea t asc t rrh t rah t asr t rad t ral t crp t cah t crp t rcd t rc row t ras t rp t csh t rsh t cas column t rac t aa t rcs t roh valid data-out t rch t oez open ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v oh v ol h or l
msm5116400d 10/14 read modify write cycle t dh t ds t oez t clz t oed t aa t oeh t rwd t cwd t cwl t rwl t cah t asc t asr t rah t rad t crp t rcd t rsh t cas t crp t cac valid data-out row t csh column t rac t oea t rcs t aw d t wp t rwc t ras t rp ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v i/oh v i/ol h or l valid data-in
msm5116400d 11/14 fast page mode cycle fast page mode write cycle (early write) t wp t rwl t wch t cwl t wp t cwl t wch t wp t wch t csh t ral t crp t dh t ds t dh t ds t dh t ds valid * data-in t wcs t wcs t wcs t asc t cah t asc t cah t rad t asr t asc t rah t rcd t crp t cas t cas t rsh t cp t cas t rp t rhpc valid * data-in valid * data-in h or l t cah t cp t pc ras v ih v il cas v ih v il address v ih v il we v ih v il dq v ih v il t rasp row column column column t cwl note: oe = h or l t pc t cas t oez t cac t off t cac t clz t oea t csh t cac t oez t rrh t rac t oea t ral t asc t cah t rcs t rch t cpa t aa t aa t rch t rcs t cah t asc t rah t rad t rcs t asr t asc t cp t cas t rsh t rasp t cas t cp t rcd t crp t clz t cah valid data-out t cpa t rp ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v oh v ol t rhcp row column column column h or l t crp t rch t aa t oea t off t oez valid data-out t clz t off valid data-out
msm5116400d 12/14 fast page mode read modify write cycle ras-only refresh cycle t asr t rah t crp t rpc t rp t ras t rc t off ras v ih v il cas v ih v il v ih v il address v oh v ol dq h or l row open note: we, oe = h or row column t aa t dh t ds t roh t cpwd t rwl t cwl t rcs column t wp t cpwd t cwd t cwl t cwd t aw d t ral t cah t crp t cp t cas t clz t cas t asc t asc t oed t dh t oez t oed t cac t oed t dh t oez t oea t aw d in t wp t ds t aa t ds column t rp t rah t rsh t asr t rad t cah out t csh t cas t rac t rasp t oez t rcs t cac t prwc t rcs t cac t clz t clz t wp t cwl t aw d t rcd t cpa t cp t oea t aa t cpa t oea t pwd t cwd t cah t asc in in ou ou ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v i/oh v i/ol h or l
msm5116400d 13/14 cas before ras refresh cycle hidden refresh read cycle ras t off t rpc t rp t rc t ras t chr t csr t rp t cp t rpc v ih v il cas v ih v il v oh v ol dq open note: we, oe, address = h or h or l t off t rac t clz t oez t roh t oea t cac t rrh t aa t ral t rcs t cah t rah t asr t asc column t rad t rp t ras t rc t rp t chr t ras t rsh t rcd t crp t rc ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v oh v ol open row valid data-out h or l
msm5116400d 14/14 hidden refresh write cycle t ds t dh t wch t ral t wp t wcs t cah t rah t asr t asc column t rad t rp t ras t rc t rp t chr t ras t rsh t rcd t crp t rc ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v ih v il row valid data-in h or l

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